Tesla has released an update to its AI accelerator roadmap, outlining plans for a sixth-generation inference chip and a successor to Dojo, its training chip. The report comes from Tom's Hardware and was published the same day the company made its announcement.
According to the company, the sixth-generation inference accelerator should deliver 80 times the compute performance of the fourth generation, which is the one in use today. The D3 training chip, for its part, will move away from an SRAM-centric architecture and adopt a multi-chiplet design with stacked HBM memory. Tesla has also started using the term 'superintelligence' instead of 'artificial intelligence' in its communications about the field, and said Dojo 3 is slated to be sent into space.
The architectural shift is the most concrete detail in the announcement. SRAM typically offers low latency but limited capacity. Stacked HBM provides far more memory and bandwidth, which matters directly for training large models. By switching to chiplets, the company also signals that it wants to rely less on a single large die, which tends to be cheaper to manufacture at scale. Still, the announcement offers targets rather than deliveries, and the performance gains will depend on validation in silicon.
For anyone buying or planning AI infrastructure, the takeaway is that Tesla is investing in its own chips for both inference and training. That is likely to put pressure on the accelerator market over the long term, but it has no immediate effect on hardware choices today. Trampolim considers the roadmap best read as a manufacturer's stated intent, and that capacity decisions should rest on products that are actually available rather than on third-party projections.